september 2000 1/9 this is preliminary information on a new product now in development. details are subject to change without notice. rev. 1.2 st7265 low-power, full-speed usb 8-bit mcu with 32k flash, 5k ram, flash card i/f, timer, pwm, adc, i 2 c data briefing n memories up to 32k of rom or flash program memory with read/write protection for flash devices, in-application program- ming (iap) via usb and in-circuit program- ming (icp) up to 5 kbytes of ram with up to 256 bytes stack n clock, reset and supply management pll for generating 48 mhz usb clock using a 12 mhz crystal low voltage reset (optional) dual supply management: analog voltage de- tector on the usb power line to enable smart power switching from usb power to battery. programmable internal voltage regulator for memory cards (2.4v to 3.3v) supplying: flash card i/o lines (voltage shifting) up to 50 ma for flash card supply clock-out capability n 47 programmable i/o lines 11 high sink i/os (10ma at 1v) 5 true open drain outputs 16 lines programmable as interrupt inputs n usb (universal serial bus) interface with dma for full speed bulk applications com- pliant with usb 12 mbs specification (version 1.1) on-chip 3.3v usb voltage regulator and transceivers with software power-down 5 usb endpoints: 1 control endpoint 2 in endpoints supporting interrupt and bulk 2 out endpoints supporting interrupt and bulk hardware conversion between usb bulk packets and 512-byte blocks n mass storage interface dtc (data transfer coprocessor): universal serial/parallel communications interface, with software plug-ins for current and future proto- col standards: 16-bit ide mode compact flash multimedia card (mmc protocol) smartmediacard secure digital card n 2 timers configurable watchdog for system reliability 16-bit timer with 2 output compare functions. n 1 communication interface i 2 c single master interface up to 400 khz n d/a and a/d peripherals pwm/brm generator (with 2 10-bit pwm/ brm outputs) 8-bit a/d converter (adc) with 2 channels n instruction set 8-bit data manipulation 63 basic instructions 17 main addressing modes 8 x 8 unsigned multiply instruction true bit manipulation n development tools full hardware/software development package device summary tqfp64 10x10 tqfp64 14x14 features st72651 st72f651 st72652 st72f652 program memory 32k rom 32k flash 16k rom 16k flash user ram (stack) - bytes 5k (256) 1k (256) peripherals usb, dtc, timer, adc, i 2 c, pwm usb, dtc, timer operating supply dual 2.4v to 5.5v or 4.0v to 5.5v (for usb) single 4.0v to 5.5v cpu frequency 6 or 3 mhz (8 mhz in usb mode) 8, 6 or 3 mhz package tqfp64 (10 x10 or 14 x14) tqfp64 (14 x14) operating temperature 0 cto+70 c 1
st7265 2/9 1 introduction the st7265 mcu supports volume data ex- change with a host (computer or kiosk) via a full speed usb interface. the mcu is capable of handing various transfer protocols, with a particu- lar emphasis on flash media card mass storage applications. st7265 is compliant with the usb mass storage class specifications, and supports related proto- cols such as bot (bulk only transfer) and cbi (control, bulk, interrupt). it is based on the st7 standard 8-bit core, with specific peripherals for managing usb full speed data transfer between the host and most types of flash media card: a full speed usb interface with serial interface engine, and on-chip 3.3v regulator and trans- ceivers. a dedicated 24 mhz data buffer manager state machine for handling 512-byte data blocks (this size corresponds to a sector both on computers and flash media cards). a data transfer coprocessor (dtc), able to handle fast data transfer with external devices. this dtc also computes the crc or ecc re- quired to handle mass storage media. an arbitration block gives the st7 core priority over the usb and dtc when accessing the data buffer. in usb mode, the usb interface is serv- iced before the dtc. a flash supply block able to provide program- mable supply voltage and i/o electrical levels to the flash media card. figure 1. usb data transfer block diagram 512-byte ram buffer 512-byte ram buffer data coprocessor data transfer buffer level shifters mass device usb sie st7 core storage transfer (dtc) arbitration usb data transfer buffer access 1
st7265 3/9 introduction (cont'd) in addition to the peripherals for usb full speed data transfer, the st7265 includes all the necess- cary features for stand-alone applications with flash mass storage. low voltage reset ensuring proper power-on or power-off of the device (selectable by option) digital watchdog 16-bit timer with 2 output compare functions. two 10-bit pwm outputs (not on all products - see device summary) fast i 2 c single master interface (not on all prod- ucts - see device summary) 8-bit analog-to-digital converter (adc) with 2 multiplexed analog inputs (not on all products - see device summary) the st72f65x are the flash versions of the st7265x in a tqfp64 package. the st7265x are the rom versions in a tqfp64 package. figure 2. digital audio player application example in play mode 512-byte ram buffer 512-byte ram buffer data coprocessor data transfer buffer level shifters mass device st7 core storage transfer (dtc) arbitration buffer access digital audio device i2c 1
st7265 4/9 introduction (cont'd) figure 3. st7265 block diagram 8-bit core alu address anddata bus oscin oscout reset data pd[7:0] or pd[3:0] (8 or 4 bits) 12mhz f cpu control ram (1/5 kbytes) program (16k/32 kbytes) memory 16-bit timer lvd watch dog v dda v pp usbdp usbdm usbvcc * not on all products (refer to table 1: device summary) transfer coprocessor port c port e port d pe[7:0] (8 bits) pc[7:0] (8 bits) pb[7:0] (8 bits) pa[7:0] (8 bits) port f pf[6:0] (7 bits) 8-bit adc* i 2 c* flash supply v ddf v ssa powe r supply dual supply usbv ss manager * block 48mhz pll clock divide r osc usb v ssf usbv dd v ss1, v ss2 v dd1, v dd2 pwm* port b port a data transfer buffer (1280 bytes) dtc s/w ram (256 bytes) regulator arbitration 1
st7265 5/9 2 pin description figure 4. 64-pin tqfp package pinout dtc / pa2 dtc / pa3 dtc / pa4 dtc / pa5 dtc / pa6 dtc / pa7 mco / pc0 dtc / pc1 dtc / pc2 dtc / pc3 v dd1 v ss1 dtc / pb6 dtc / pb7 dtc / pa0 dtc / pa1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ei1 ei0 usbv dd v ddf v ssf dtc / pe5 (hs) dtc / pe6 (hs) dtc / pe7 (hs) dtc / pb0 dtc / pb1 dtc / pb2 dtc / pb3 dtc / pb4 dtc / pb5 usbv ss usbdm usbdp usbvcc pd7 pd6 pd5/ocmp2 pd4/ocmp1 pd3 pd2 pd1 pd0 pc7 pc6 pc5 pc4 pe3 / pwm0 / dtc pe2 (hs) / dtc pe1 (hs) / dtc pe0 (hs) / dtc v dda v dd2 pf6 (hs) pf5 (hs) pf4 (hs) / us- pf3 / ain1 pf2 / ain0 pf1 (hs) / sda pf0 (hs) / scl reset v pp pe4 / pwm1 oscout oscin v ss2 v ssa (hs) 10ma high sink capability ei x associated external interrupt vector i/o pin supplied by v ddf /v ssf 1
st7265 6/9 pin description (cont'd) legend / abbreviations: type: i = input, o = output, s = supply v ddf powered: i/o powered by the alternate sup- ply rail, supplied by v ddf and v ssf . in/output level: c t = cmos 0.3v dd /0.7v dd with input trigger output level: hs = 10ma high sink (on n-buffer only) port and control configuration: input:float = floating, wpu = weak pull-up, int = in- terrupt output: od = open drain, t = true open drain, pp = push-pull, op = pull-up enabled by option byte. refer to ai/o port implementationo on page 51 of the datasheet for more details on the software configuration of the i/o ports. the reset configuration of each pin is shown in bold. table 1. device pin description pin pin name type v ddf powered level port / control main function (after reset) alternate function tqfp64 input output input output float wpu int od pp 1 usbv ss s usb digital ground 2 usbdm i/o usb bidirectional data (data -) 3 usbdp i/o usb bidirectional data (data +) 4 usbvcc o usb power supply, output by the on-chip usb 3.3v linear regulator. 5 usbv dd s usb power supply voltage (4v - 5.5v) 6v ddf sx power line for alternate supply rail. can be used as input (with external supply) or output (when using the on-chip voltage regulator). note: an external decoupling capacitor (min. 20nf) must be connected to this pin to stabilize the regulator. 7v ssf sx ground line for alternate supply rail. can be used as input (with external supply) or output (when using the on-chip voltage regulator) 8 pe5/dtc i/o x c t hs x 2 x 2 x port e5 dtc i/o with serial capability (mmc_cmd) 9 pe6/dtc i/o x c t hs x x x port e6 dtc i/o with serial capability (mmc_dat) 10 pe7/dtc i/o x c t hs x x x port e7 dtc i/o with serial capability (mmc_clk) 11 pb0/dtc i/o x ct x x port b0 dtc 12 pb1/dtc i/o x ct x x port b1 dtc 13 pb2/dtc i/o x ct x x port b2 dtc 14 pb3/dtc i/o x ct x x port b3 dtc 15 pb4/dtc i/o x ct x x port b4 dtc 16 pb5/dtc i/o x ct x x port b5 dtc 17 pb6/dtc i/o x ct x x port b6 dtc 1
st7265 7/9 18 pb7/dtc i/o x ct x x port b7 dtc 19 pa0/dtc i/o x ct x ei0 x x port a0 dtc 20 pa1/dtc i/o x ct x x x port a1 dtc 21 pa2/dtc i/o x ct x x x port a2 dtc 22 pa3/dtc i/o x ct x x x port a3 dtc 23 pa4/dtc i/o x ct x x x port a4 dtc 24 pa5/dtc i/o x ct x x x port a5 dtc 25 pa6/dtc i/o x ct x x x port a6 dtc 26 pa7/dtc i/o x ct x x x port a7 dtc 27 pc0/mco i/o x ct x x port c0 main clock output 28 pc1/dtc i/o x c t x x port c1 dtc i/o with serial capability (datarq) 29 pc2/dtc i/o x c t x x port c2 dtc i/o with serial capability (sdat) 30 pc3/dtc i/o x c t x x port c3 dtc i/o with serial capability (sclk) 31 v dd1 s power supply voltage (2.4v - 5.5v) 32 v ss1 s digital ground 33 pc4/dtc i/o c t x x port c4 dtc 34 pc5/dtc i/o c t x x port c5 dtc 35 pc6/dtc i/o c t x x port c6 dtc 36 pc7/dtc i/o c t x x port c7 dtc 37 pd0 i/o ct x ei1 x x port d0 38 pd1 i/o ct x x x port d1 39 pd2 i/o ct x x x port d2 40 pd3 i/o ct x x x port d3 41 pd4/ocmp1 i/o ct x x x port d4 timer output compare 1 42 pd5/ocmp2 i/o ct x x x port d5 timer output compare 2 43 pd6 i/o ct x x x port d6 44 pd7 i/o ct x x x port d7 45 pe0/dtc i/o ct hs x x port e0 dtc 46 pe1/dtc i/o c t hs x x port e1 dtc 47 pe2/dtc i/o c t hs x x port e2 dtc 48 pe3/dtc/pwm0 i/o c t x x port e3 dtc / pwm output 0 pin pin name type v ddf powered level port / control main function (after reset) alternate function tqfp64 input output input output float wpu int od pp
st7265 8/9 1 if the peripheral is present on the device (see table ) 2 a weak pull-up can be enabled on pe5 input and open drain output by configuring the peor register and depending on the pe5pu bit in the option byte. 49 pe4/pwm1 i/o c t x x port e4 pwm output 1 50 v pp s flash programming voltage. must be held low in normal operating mode. 51 reset i/o x x bidirectional. this active low signal forces the initialization of the mcu. this event is the top priority non maskable interrupt. this pin is switched low when the watchdog has triggered or v dd is low. it can be used to reset external peripherals. 52 pf0 / scl i/o c t hs x t port f0 i 2 c serial clock 1 53 pf1 / sda i/o c t hs x t port f1 i 2 c serial data 1 54 pf2 / ain0 i/o c t x x port f2 analog input 0 1 55 pf3 / ain1 i/o c t x x port f3 analog input 1 1 56 pf4 / usben i/o c t hs x t port f4 usb power management usb enable (alternate function se- lected by option bit) 57 pf5 i/o c t hs x t port f5 58 pf6 i/o c t hs x t port f6 59 v dd2 s main power supply voltage (2.4v - 5.5v) 60 v dda s analog supply voltage 61 v ssa s analog ground 62 v ss2 s digital ground 63 oscin i input/output oscillator pins. these pins con- nect a 12 mhz parallel-resonant crystal, or an external source to the on-chip oscillator. 64 oscout o pin pin name type v ddf powered level port / control main function (after reset) alternate function tqfp64 input output input output float wpu int od pp 1
st7265 9/9 notes: information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain sweden - switzerland - united kingdom - u.s.a. http:// www.st.com
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